1. Field of the Invention
The present invention relates to the layout of a semiconductor memory and a content-addressable memory, and more particularly to the layout of a semiconductor memory and a content-addressable memory adaptable for size reduction, high-speed operation and power saving.
2. Description of the Prior Art
Existing semiconductor memories are generally characterized by a large storage capacity, memory arrays divided into blocks and hierarchical address decoders. In the case of a content-addressable memory (hereinafter called CAM) on the analogy with the semiconductor memory, the address encoder is also rendered hierarchical. A description will subsequently be given of the conventional layout of a semiconductor memory or CAM, and problems arising therefrom.
FIG. 9 is a block diagram showing the layout of a conventional static random access memory (SRAM). In the layout of this SRAM 100, a memory array 102 comprises a plurality of memory blocks 102a, 102b, . . . similar in structure, whereas an address decoder 104 is made hierarchical so as to include a main decoder 106 and a subdecoder 108. In each of the memory blocks 102a, 102b, . . . exist a row of memory cells of the same memory ward 116 and a column of memory wards. Moreover, the same main ward signal is supplied from the main decoder 106 via main ward lines 110a, 110b, . . . to similar memory wards 116 of all the memory blocks 102a, 102b, . . . , whereas different block selection signals (hereinafter called the block signal(s)) are supplied from the subdecoder 108 via memory block selection lines (hereinafter simply called the block line(s)) 112a, 112b, . . . to the respective memory blocks 102a, 102b, . . . Incidentally, each block in this block diagram is exemplarily shown, using buffers and AND gates.
When an address signal is supplied from the outside to the address decoder 104 in the SRAM 100 thus configured, a high order bit, for example, is decoded by the subdecoder 108, and one of the block signals each applied to the memory blocks 102a, 102b, . . . becomes active. Further, a low order bit, for example, is decoded by the main decoder 106, and one of the main ward signals commonly applied to similar memory wards 116 of all the memory blocks 102a, 102b, . . . becomes active. In each memory ward 116, the main ward signal and the block signal are ANDed, and the ward signal is supplied via a subward line 128. Thus any desired memory ward 116 is selected by supplying the address signal from outside the SRAM 100.
FIG. 10 is a block circuit diagram of a memory ward of the aforesaid SRAM. This memory ward 116 comprises a plurality of memory cells 41-1, 41-2, . . . , 41-n similar in structure. Each of the memory cells 41-1, 42-2, . . . , 41-n is provided with a first inverter 20-1 (20-2, . . . , 20-n) and a second inverter 21-1 (21-2, . . . , 21-n), the output and input of the former being connected to the input and output of the latter, respectively. With these pairs of inverters 20-1, 21-1; 20-2, 21-2; . . . ; 20-n, 21-n, 1-bit logical data "1" or "0" is stored in each memory cell 41-1 (42-2, . . . , 41-n).
In each of the memory cells 41-1, 42-2, . . . , 41-n, the output of the first inverter 20-1 (20-2, . . . , 20-n) is connected via an N-channel transistor 22-1 (22-2, . . . , 22-n) to a bit line 23-1 (23-2, . . . , 23-n), and the gates of these transistors 22-1, 22-2, . . . 22-n are connected to the subward line 128. Similarly, the output of the second inverter 21-1 (21-2, . . . , 21-n) is connected via an N-channel transistor 25-1 (25-2, . . . , 25-n) to a bit bar line 26-1 (26-2, . . . , 26-n), and the gates of these transistors 25-1, 25-2, . . . , 25-n are also connected to the subward line 128.
When, for example, logical data "1" (logical "1" on the output side of the first inverter 20-1, and logical "0" on the output side of the second inverter 21-1) is written to the memory cell 41-1 in the memory ward 116 thus configured, signals of logical "1" and logical "0" are respectively applied to the bit line 23-1 and the bit bar line 26-1 to render the subward line 128 active (logical "1") by supplying from outside the SRAM 100 an address signal for the memory ward 116 to be selected as stated above. Then the signals on the bit line 23-1 and the bit bar line 26-1 are supplied via the respective transistors 22-1, 25-1 and stored in the two inverters 20-1, 21-1.
When, for example, the logical data "0" (logical "0" on the output side of the first inverter 20-2, and logical "1" on the output side of the second inverter 21-2) stored in the memory cell 41-2 as shown in FIG. 10 is read, both the bit line 23-2 and the bit bar line 26-2 are precharged to uniformize their potentials to render the subward line 128 active by supplying from outside the SRAM 100 the address signal for the memory ward 116 to be selected as stated above. Thus a signal of logical "0" stored in the memory cell 41-2 is transmitted via the respective transistors 22-2, 25-2 to the bit line 23-2 and the bit bar line 26-2. Then the bit line 23-2 is discharged and the potential difference between the bit line 23-2 and the bit bar line 26-2 is detected by a sense amplifier (not shown), whereby the data stored in the memory cell 41-2 is read out. The above writing and reading operations are normally performed with one memory ward as a unit.
In the layout of the aforementioned conventional SRAM 100, the same main ward line is commonly input to similar memory wards 116 of all the memory blocks 102a, 102b, . . . , that is, the main ward line 110a (110b, . . . ) is in the form of, for example, metal wiring so that it is passed through a layout area equivalent in height to the layout of one memory ward 116. Therefore, a wiring forming area has been necessitated. By this is meant is that not only a SRAM but also a memory array is formed in blocks, which is common to semiconductor memories having hierarchical address decoders.
A description will subsequently be given of CAM by way of example. Like the SRAM, a Content-Addressable Memory or CAM has a storage unit for storing data, and a retrieval unit for retrieving the data stored in the storage unit. Retrieval data is prestored in the storage unit and when the data stored in the storage unit matches retrieval data, match-data retrieval is carried out in the retrieval unit from which the presence or absence of hit data (coincident data), the stored address and the like are retrieved and output in a single cycle. The CAM is used to improve the performance of a system in which the retrieval process is frequently performed because the use of such a CAM makes it possible to instantly obtain any one of the intended data from an intensive collection of data.
FIG. 11 is a block diagram showing the layout of a conventional CAM. In the layout of this CAM 134, a memory array 136 comprises a plurality of memory blocks 136a, 136b, . . . similar in structure, whereas as in the aforesaid SRAM 100, an address decoder (not shown) is made hierarchical so as to include a main decoder and a subdecoder. Further, a priority encoder 138 is made hierarchical so as to include a main priority encoder 140 and a subpriority encoder 142. Incidentally, each block in this block diagram is exemplarily shown, using buffers and AND gates.
In each of the memory blocks 136a, 136b, . . . exist a row of memory cells of the same memory ward 152 and a column of memory wards. A hit signal is supplied via a match line 144 to each memory ward 152, and each match line 144 is subjected to wired connection via a tri-state gate 146 to a feed line 148a (148b, . . . ) in each similar memory ward 152 of all the memory blocks 136a, 136b. Moreover, the hit signal is supplied to the main priority encoder 40 via the feed line 148a (148b, . . . ) so wired as to straddle across every similar memory ward 152 of all the memory blocks 136a, 136b, . . . From the subpriority encoder 142, an enable signal for controlling ON/OFF of the tri-state gate 146 subjected to wired connection to the feed line 148a (148b, . . . ) is supplied via an enable line 150a (150b, . . . ) to each of the memory blocks 136a, 136b, . . .
When retrieval data is fed from outside the CAM 134 thus configured, the hit signal is generated in the memory ward 152 in which hit data is stored. The hit signal generated in each memory ward 152 and ORed (though not shown) in each of the memory blocks 136a, 136b, . . . is supplied to the subpriority encoder 142 from which an active enable signal is supplied via the enable line 150a (150b, . . . ) to only what is given the highest priority according to the order of priority from among the memory blocks 136a, 136b, . . . in which the hit signal has been generated.
In the memory block supplied with the active enable signal, the tri-state gate 146 which subjects the match line 144 and the feed line 148a (148b, . . . ) to wired connection is turned on, and the hit signal generated in each memory ward 152 is supplied via the feed line 148a (148b, . . . ) to the main priority encoder 140. Then an address corresponding to what is given the highest priority according to the order of priority from among the memory wards 152 in which the hit signal has been generated is encoded in the main priority encoder 140. By feeding retrieval data from outside the CAM 134, the address of the memory ward where data matching the retrieval data is stored can thus be encoded and output.
FIG. 12 is a block circuit diagram of a (AND type) memory ward of the aforesaid CAM, wherein like reference characters designate like and corresponding elements of the circuit shown in FIG. 10 and only points of difference will be described.
The memory ward 152 shown in FIG. 12 is provided with the following elements in addition to those of the memory ward 116 shown in FIG. 10. In each of the memory cells 11-1, 11-2, . . . , 11-n, two N-channel transistors 27-1, 28-1 (27-2, 28-2; . . . ; 27-n, 28-n) connected in series are arranged so as to couple the bit line 23-1 (23-2, . . . , 23-n) and the bit bar line 26-1 (26-2, . . . , 26-n) together. Further, the gate of the transistor 27-1 (27-2, . . . , 27-n) is connected to the output of the first inverter 20-1 (20-2, . . . , 20-n), whereas the gate of the transistor 28-1 (28-2, . . . , 28-n) is connected to the output of the second inverter 21-1 (21-2, . . . , 21-n).
Moreover, the memory ward 152 is provided with the match line 144 extending and straddling over the plurality of memory cells 11-1, 11-2, . . . , 11-n constituting the memory ward 152. The match line 144 is equipped with N-channel transistors 36-1, 36-2, . . . , 36-n each corresponding to the memory cells 11-1, 11-2, . . . , 11-n. These transistors 36-1, 36-2, . . . , 36-n are connected in series, and the gate of each transistor is connected to the median point between the two transistors 27-1, 28-1 (27-2, 28-2; . . . ; 27-n). Further, the right end of the match line 144 shown in FIG. 12 is connected to the drain of a P-channel transistor 32 whose source is connected to a power supply, whereas the left end thereof as shown therein is connected to the drain of an N-channel transistor 36-0 whose source is grounded. Further, a control line 30 is connected to the gates of the transistors 32, 36-0, and the right end of the match line 144 is also input to an inverter 31.
Coincident retrieval, which will be described below, is carried out in the content-addressable memory having the memory ward 152 so configured as shown in FIG. 12 and a peripheral circuit.
First, it is assumed that logical data "1" is stored in the memory cell 11-1, that is, logical "1" is to be retrieved from the memory cell 11-1 in such a state that the output side of the first inverter 20-1 is logical "1", whereas the output side of the second inverter 21-1 is logical "0".
In other words, the subward line 128 is held in the state of logical "0" and the bit line 23-1 is in the state of logical "1" and besides the bit bar line 26-1 is in the state of logical "0". In this case, a voltage of logical "1" is applied to the gate of the transistor 27-1, and a logical "1" signal on the bit line 23-1 is applied to the gate of the transistor 36-1, whereby the transistor 36-1 is turned on; that is, when the data stored in the memory cell 11-1 matches retrieval data supplied via the bit line 23-1 and the bit bar line 26-1, the corresponding transistor 36-1 is turned on.
Subsequently, it is assumed that logical data "0" is stored in the memory cell 11-2, that is, logical "1" is also to be retrieved from the memory cell 11-2 in such a state that the output side of the first inverter 20-2 is logical "0", whereas the output side of the second inverter 21-2 is logical "1".
In other words, the subward line 128 is held in the state of logical "0" and the bit line 23-2 is in the state of logical "1" and besides the bit bar line 26-2 is in the state of logical "0". In this case, a logical "0" signal on the bit bar line 26-2 is applied via the transistor 28-2 to the gate of the transistor 36-2, whereby the transistor 36-2 is held OFF. In the case of inequality, the charge precharged in the match line 144 is not discharged accordingly.
In order to mask a certain memory cell, the logical "0" of the subward line 128 is left unchanged and logical "1" is established on both the bit line 23-n and the bit bar line 26-n as shown in the memory cell 11-n. In this case, either transistor 27-n or 28-n is turned on, depending on which one of the logical data "1" and "0" is stored in the memory cell 11-1, whereby the signal of logical "1" is applied to the gate of the transistor 36-n in either case. The transistor 36-n is then turned on.
At the time of retrieval, the control line 30 is first set to logical "0" and the transistor 32 is turned on, and further the match line 144 on the input side of the inverter 31 is precharged. Then the control line 30 is set to logical "1", and the transistor 32 is turned off and released from the precharged condition, whereas the transistor 36-0 is turned on. When the data stored in the memory ward 152 matches retrieval data over all the memory cells 11-1, 11-2, . . . , 11-n constituting the memory ward 152 (the aforesaid mask bit is regarded identical), all the transistors 36-1, 36-2, . . . , 36-n are turned on and the charge precharged in the match line 144 is discharged. A hit signal of logical "1" is output from the inverter 31.
In the case of the structure shown in FIG. 12, the match line 144 in each memory ward 152 is simultaneously precharged prior to retrieval, and all the transistors 36-1, 36-2, . . . , 36-n are turned on only when the data stored in the memory ward 152 matches retrieval data at the time of retrieval. Then the charge precharged via these transistors 36-1, 36-2, . . . , 36-n is discharged and the hit signal is generated, whereby it is considered that match retrieval has been fulfilled.
FIG. 13 is a block circuit diagram of a (OR type) memory ward of the aforesaid CAM, wherein like reference characters designate like and corresponding component elements of the circuit shown in FIG. 10 and only points of difference will be described.
A memory ward 168 of FIG. 13 is provided with the following elements in addition to those of the memory ward 116 shown in FIG. 10. This memory ward 168 is equipped with the match line 144 and an identity retrieval control line 178 extending and straddling over the plurality of memory cells 11-1, 11-2, . . . , 11-n constituting the memory ward 168. In each of the memory cells 11-1, 11-2, . . . , 11-n, two pairs of N-channel transistors 60-1 and 62-1, 62-1 and 63-1 (60-2 and 61-2, 62-2 and 63-2; . . . ; 60-n and 61-n, 62-n and 63-n) connected in series are arranged so as to couple the match line 144 and the identity retrieval control line 178 together. Further, the gate of the transistor 60-1 (60-2, . . . , 60-n) is connected to the output of the second inverter 20-1 (21-2, . . . , 21-n); the gate of the transistor 61-1 (61-2, . . . , 61-n) to the output of the bit line 23-1 (23-2, . . . , 23-n); the gate of the transistor 62-1 (62-2, . . . , 62-n) to the first inverter 20-1 (20-2, . . . , 20-n); and the gate of the transistor 63-1 (63-2, . . . , 63-n) to the bit bar line 26-1 (26-2, . . . , 26-n).
Further, the right end of the match line 144 shown in FIG. 13 is connected to the drain of the P-channel transistor 32 whose source is connected to the power supply, whereas the left end thereof as shown therein is connected to the drain of an N-channel transistor 160 whose source is grounded. Further, a control line 162 is connected to the gates of the transistors 32, 160, and the right end of the match line 144 is also input to the inverter 31.
Match retrieval, which will be described below, is carried out in the content-addressable memory having the memory ward 168 so configured as shown in FIG. 13 and a peripheral circuit.
First, it is assumed that logical data "1" is stored in the memory cell 11-1, that is, logical "1" is to be retrieved from the memory cell 11-1 in such a state that the output side of the first inverter 20-1 is logical "1", whereas the output side of the second inverter 21-1 is logical "0".
In other words, the subward line 128 is held in the state of logical "0" and the bit line 23-1 is in the state of logical "1" and besides the bit bar line 26-1 is in the state of logical "0". In this case, the two pairs of transistors 60-1 and 61-1, 62-1 and 63-1 are kept "ON and OFF" and "OFF and ON", respectively; that is, when the data stored in the memory cell 11-1 matches retrieval data supplied via the bit line 23-1 and the bit bar line 26-1, the two pairs of transistors 60-1 and 61-1, 62-1 and 63-1 connected in series are totally turned off, and the match line 144 and the identity retrieval control line 178 are not electrically connected.
Subsequently, it is assumed that logical data "0" is stored in the memory cell 11-2, that is, logical "1" is also to be retrieved from the memory cell 11-2 in such a state that the output side of the first inverter 20-2 is logical "0", whereas the output side of the second inverter 21-2 is logical "1".
In other words, the subward line 128 is held in the state of logical "0" and the bit line 23-2 is in the state of logical "1" and besides the bit bar line 26-2 is in the state of logical "0". In this case, the two pairs of transistors 60-2 and 61-2, 62-2 and 63-2 connected in series are turned "ON and ON" and turned "OFF and OFF", respectively; that is, one of the two pairs of transistors 60-2 and 61-2, 62-2 and 63-2 connected in series are turned on in the case of inequality, and the match line 144 and the identity retrieval control line 178 are electrically connected.
In order to mask a certain memory cell, the logical "0" of the subward line 128 is left unchanged and logical "1" is established on both the bit line 23-n and the bit bar line 26-n as shown in the memory cell 11-n. In this case, both the two pairs of transistors 60-n and 61-n, 62-n and 63-n connected in series are turned off, irrespective of the data stored in the memory cell 11-n since both the transistors 61-n, 63-n are turned off, and the match line 144 and the identity retrieval control line 178 are not electrically connected.
At the time of retrieval, the control line 162 is first set to logical "0" and the transistor 32 is turned on, and further the match line 144 is precharged. Then the control line 162 is set to logical "1", and the transistor 32 is turned off and released from the precharged condition, whereas the transistor 160 is turned on, so that the identity retrieval control line 178 is electrically connected to the ground. When the data stored in the memory cells 11-1, 11-2, . . . , 11-n matches retrieval data over all the memory cells 11-1, 11-2, . . . , 11-n constituting the memory ward 168 (the aforesaid mask bit is regarded identical), all the two pairs of transistors 60-1 and 62-1, 63-1 and 63-1; 60-2 and 61-2, 62-2 and 63-2; . . . ; 60-n and 61-n, 62-n and 63-n connected in series are totally turned off. As the charge precharged in the match line 144 is not discharged, a hit signal of logical "0" is output from the inverter 31.
In the case of the structure shown in FIG. 13, the match line 144 in each memory ward 168 is simultaneously precharged prior to retrieval, and all the two pairs of transistors 60-1 and 62-1, 63-1 and 63-1; 60-2 and 61-2, 62-2 and 63-2; . . . ; 60-n and 61-n, 62-n and 63-n connected in series are turned off only when the data stored in the memory cells 11-1, 11-2, . . . , 11-n of the memory ward 168 matches retrieval data at the time of retrieval. Then the match line 144 is cut off the identity retrieval control line 178 and the charge thus precharged is not discharged, whereby the hit signal is generated. Thus match retrieval is considered to be fulfilled.
In the layout of the aforesaid conventional CAM, the same feed line, like the main ward line in the aforementioned SRAM, is used to wire similar memory wards of all the memory blocks. In other words, the feed line is in the form of metal wiring so that it is passed through an area equivalent in height to the layout of one memory ward. Therefore, a wiring forming area has been necessitated.